t e e h s a t a d 2b 2 1 . 0 8 1 6 2 8-bi t l a t c h e d dmos p ow e r drive r the a 6 b2 7 3ka a n d a 6b 27 3 k lw c o mbi n e ei gh t (p o s itive - edge - t r ig g e r e d d- ty p e ) d ata latc h e s and dmos ou tput s for sys tem s r e q ui r in g r elati v el y h i gh l o a d po w e r. dr i v e r a pp licati ons i n cl ud e r ela ys , s ole - n oi ds, an d othe r me d ium - c urr e n t o r h i g h -v olta g e p e r i p he r al p ow e r l o a ds . t h e cmos in p ut s an d latche s all ow d i r ect i n te rf acin g w it h mic r o pro ce ss o r- ba s ed sys tem s. us e w ith ttl ma y r e qu i r e a p p r o pr iat e p ull - u p r e s i s t ors t o e nsur e an i n put l o gic hi gh . the dmos o ut pu t in v e r t s the da t a i n p u t . a ll o f the out p u t dr i v e rs a r e d i s a b le d ( the dmos s in k d r i v e rs t urn e d off) w ith th e c le a r i n p u t l ow. t h e a 6 b2 73 ka / k lw dmos o p e n-dr ain outp u t s a r e ca p a b le of s in k in g up t o 50 0 m a . s imila r de v ice s w ith r e du ce d r ds( on ) a r e a v aila b le a s t h e a62 7 3ka / k lw . the a 6 b2 7 3ka i s f u rn i sh ed i n a 2 0-p i n d u al i n- line p la s ti c p ac k age. t h e a6b 27 3k lw i s fur ni sh e d i n a 2 0- lead w ide -b od y , s mall - o u tline pla s tic pac k age (soic) w it h g u ll -w ing lea ds f o r s u rf ace - m o u n t a p plicatio ns. c op pe r lead fr ame s, r e d uced sup pl y cu rr en t r e qu i r eme n t s , and lo w o n-s tate r e s i s tance allo w bot h de v ice s to s in k 1 5 0 m a fro m all o ut pu t s c on tinu ous l y , t o am b ie n t tem p e r atu r e s ove r 8 5 c . features 5 0 v m inim u m ou tp u t clamp v olta g e 1 5 0 m a o ut pu t c urr e n t ( all o u t p ut s s im u lta n e ous l y ) 5 ? t yp ical r ds( on ) lo w p o w e r co n s um p ti o n r eplaceme n t s f o r t pic 6b 27 3 n a n d t pi c 6b 27 3d w 6b27 3 no te t h at the a 6b273 ka (dip) and the a6 b 2 7 3k l w (soi c ) a r e elect r ically identical an d s ha r e a comm o n te r minal numbe r a ss ignment . 1 2 3 8 9 13 14 15 16 17 19 4 5 6 7 12 18 20 in v d d groun d ou t 8 ou t 7 ou t 6 dwg. pp-015-2 a ou t 1 ou t 2 ou t 3 ou t 4 ou t 5 10 11 clear l ogi c supply strob e 8 in 7 in 6 in 5 in 4 in 3 in 2 in 1 latches latches absolute maximum ratings at t a = 2 5 c ou t p ut v olta g e, v o ............................... 50 v o utp u t dr ain c u rr e n t , c o ntinuo us, i o .......................... 150 m a * p ea k , i o m ................................... 500 ma ? s in g le -pu l s e a valanche ene r gy , e a s ................................................. 30 m j l o gic su p p ly v olta g e, v d d .................. 7.0 v in put v olta g e ra n ge , v i ................................... -0 .3 v t o +7 . 0 v p ac k age p o w e r d i ss ipation , p d ........................................... s ee gra p h op e r ating tempe r at ur e r a n ge , t a ................................. -4 0 c t o +12 5 c s t or age tem p e r atu r e range , t s ................................. -5 5 c t o +15 0 c * each o utput, all output s on . ? pu l s e d ur ation 100 s , duty cycle 2% . cau ti on: th e s e cmos d evice s ha ve i npu t s t a ti c pro tecti on (c l ass 3) bu t ar e s till sus ce p ti b le t o damag e i f ex pos e d t o ext r e m ely h i gh s t a tic elect r ic a l c harg e s . selection guide part number pb-free* package packing r ja (c/w) a6b273k l w -t y es 20-pin soicw 37 per tube 70 a6b273k l wtr-t y es 20-pin soicw 1000 per reel 70 r jc (c/w) 17 17 *pb-based variants are being phased out of the product line. some variants cited in this footnote are in production but have been determined to be last time buy or not for new design. this classification indicates that sale of this device is currently restricted to existing customer applications. the variants should not be purchased for new design applications because obsolescence in the near future is probable. samples are no longer available. status change for last time buy: october 31, 2006. deadline for receipt of last time buy orders: april 27, 2007. these variants include: a6b273k l w and a6b273k l wtr. status change for not for new design: may 1, 2006. these variants include: a6b273ka.
6b273 8-bit latched dmos power driver 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 w copyright ?2002 allegro microsystems, inc. logic symbol c1 r 1d 4 5 6 7 14 15 16 17 1 2 11 dw g . fp-046-1a 1d 3 1d 8 1d 9 1d 12 1d 13 1d 18 1d 19 50 75 100 125 150 2.5 0.5 0 allowable package power dissipation in watts ambient temperature in c 2.0 1.5 1.0 25 dwg. gs-004b suffix 'lw', r = 90 c/w ja suffix 'a', r = 55 c/w ja function table inputs clear strobe in x out x lxxh hhl hlh hlxr l = low logic level h = high logic level x = irrelevant r = previous state dmos power driver output logic inputs in dwg. ep-010-16 v dd dwg. ep-063 out
6b273 8-bit latched dmos power driver www.allegromicro.com functional block diagram ground dwg. fp-016-2 clear (active low) v dd logic supply out 1 d c1 clr out 2 d c1 clr out 3 d c1 clr out 4 d c1 clr out 5 d c1 clr out 6 d c1 clr out 7 d c1 clr out 8 d c1 clr 1 in 2 in 3 in 4 in 5 in 6 in 7 in 8 in strobe
6b273 8-bit latched dmos power driver 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 limits characteristic symbol test conditions min. typ. max. units logic supply voltage v dd operating 4.5 5.0 5.5 v output breakdown v (br)dsx i o = 1 ma 50 v voltage off-state output i dsx v o = 40 v, v dd = 5.5 v 0.1 5.0 a current v o = 40 v, v dd = 5.5 v, t a = 125 c 0.15 8.0 a static drain-source r ds(on) i o = 100 ma, v dd = 4.5 v 4.2 5.7 ? on-state resistance i o = 100 ma, v dd = 4.5 v, t a = 125 c 6.8 9.5 ? i o = 350 ma, v dd = 4.5 v (see note) 5.5 8.0 ? nominal output i on v ds(on) = 0.5 v, t a = 85 c90ma current logic input current i ih v i = v dd = 5.5 v 1.0 a i il v i = 0, v dd = 5.5 v -1.0 a prop. delay time t plh i o = 100 ma, c l = 30 pf 150 ns t phl i o = 100 ma, c l = 30 pf 90 ns output rise time t r i o = 100 ma, c l = 30 pf 200 ns output fall time t f i o = 100 ma, c l = 30 pf 200 ns supply current i dd(off) v dd = 5.5 v, outputs off 20 100 a i dd(on) v dd = 5.5 v, outputs on 150 300 a typical data is at v dd = 5 v and is for design information only. note ?pulse test, duration 100 s, duty cycle 2%. electrical characteristics at t a = +25 c, v dd = 5 v, t ir = t if 10 ns (unless otherwise specified). recommended operating conditions over operating temperature range logic supply voltage range, v dd ............... 4.5 v to 5.5 v high-level input voltage, v ih ............................ 0.85v dd low-level input voltage, v il ................................. 0.15v dd
6b273 8-bit latched dmos power driver www.allegromicro.com timing requirements phl t 90% f t 50% su(d) t plh t 50% outputx dwg. wp-036-1 10% r t inx strobe h(d) t 50% su(d) t h(d) t input active time before strobe (data set-up time), t su(d) .............................................. 20 ns input active time after strobe (data hold time), t h(d) ................................................... 20 ns input pulse width, t w(d) ....................................................... 40 ns input logic high, v ih ................................................ 0.85v cc input logic low, v il ................................................. 0.15v cc test circuits 10.5 ? +15 v out 200 mh dut dwg. ep-066 input i o v o t av i as = 500 ma v (br)dsx v o(on) single-pulse avalanche energy test circuit and waveforms e as = i as x v (br)dsx x t av /2
6b273 8-bit latched dmos power driver 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 terminal descriptions terminal no. terminal name function 1 clear when (active) low, all latches are reset and all outputs go high (turn off). 2 in 1 cmos data input to a latch. when strobed, the output then inverts the data input (in 1 = high, out 1 = low). 3 in 2 cmos data input to a latch. when strobed, the output then inverts the data input (in 2 = high, out 2 = low). 4 out 1 current-sinking, open-drain dmos output. 5 out 2 current-sinking, open-drain dmos output. 6 out 3 current-sinking, open-drain dmos output. 7 out 4 current-sinking, open-drain dmos output. 8 in 3 cmos data input to a latch. when strobed, the output then inverts the data input (in 3 = high, out 3 = low). 9 in 4 cmos data input to a latch. when strobed, the output then inverts the data input (in 4 = high, out 4 = low). 10 ground reference terminal for all voltage measurements. 11 strobe a cmos dynamic input to all latches. data on each in x terminal is loaded into its associated latch on a low-to-high strobe transition. 12 in 5 cmos data input to a latch. when strobed, the output then inverts the data input (in 5 = high, out 5 = low). 13 in 6 cmos data input to a latch. when strobed, the output then inverts the data input (in 6 = high, out 6 = low). 14 out 5 current-sinking, open-drain dmos output. 15 out 6 current-sinking, open-drain dmos output. 16 out 7 current-sinking, open-drain dmos output. 17 out 8 current-sinking, open-drain dmos output. 18 in 7 cmos data input to a latch. when strobed, the output then inverts the data input (in 7 = high, out 7 = low). 19 in 8 cmos data input to a latch. when strobed, the output then inverts the data input (in 8 = high, out 8 = low). 20 logic supply (v dd ) the logic supply voltage (typically 5 v).
6b273 8-bit latched dmos power driver www.allegromicro.com a6b273ka dimensions in inches (controlling dimensions) dimensions in millimeters (for reference only) notes: 1. exact body and lead configuration at vendor? option within limits shown. 2. lead spacing tolerance is non-cumulative. 3. lead thickness is measured at seating plane or below. 4. supplied in standard sticks/tubes of 18 devices. 0.014 0.008 0.300 bsc dwg. ma-001-20 in 0.430 max 20 1 10 0.280 0.240 0.210 max 0.070 0.045 0.015 min 0.022 0.014 0.100 bsc 0.005 min 0.150 0.115 11 1.060 0.980 0.355 0.204 7.62 bsc dwg. ma-001-20 mm 10.92 max 20 1 10 7.11 6.10 5.33 max 1.77 1.15 0.39 min 0.558 0.356 2.54 bsc 0.13 min 3.81 2.93 11 26.92 24.89
6b273 8-bit latched dmos power driver 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 a6b273klw dimensions in inches (for reference only) dimensions in millimeters (controlling dimensions) 0 to 8 1 2 3 0.020 0.013 0.0040 min. 0.0125 0.0091 0.050 0.016 dwg. ma-008-20 in 0.050 bsc 20 11 0.2992 0.2914 0.419 0.394 0.5118 0.4961 0.0926 0.1043 0 to 8 1 20 2 3 0.51 0.33 0.10 min. dwg. ma-008-20 mm 1.27 bsc 11 0.32 0.23 1.27 0.40 7.60 7.40 10.65 10.00 13.00 12.60 2.65 2.35 notes: 1. exact body and lead configuration at vendor s option within limits shown. 2. lead spacing tolerance is non-cumulative. 3. supplied in standard sticks/tubes of 37 devices or add tr to part number for tape and reel.
6b273 8-bit latched dmos power driver www.allegromicro.com the products described here are manufactured under one or more u.s. patents or u.s. patents pending. allegro microsystems, inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. the information included herein is believed to be accurate and reliable. however, allegro microsystems, inc. assumes no responsi- bility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.
6b273 8-bit latched dmos power driver 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 power interface drivers function output ratings* part number ? serial-input latched drivers 8-bit (saturated drivers) -120 ma 50 v? 5895 8-bit 350 ma 50 v 5821 8-bit 350 ma 80 v 5822 8-bit 350 ma 50 v? 5841 8-bit 350 ma 80 v? 5842 8-bit (constant-current led driver) 75 ma 17 v 6275 8-bit (constant-current led driver) 120 ma 24 v 6277 8-bit (dmos drivers) 250 ma 50 v 6595 8-bit (dmos drivers) 350 ma 50 v? 6a595 8-bit (dmos drivers) 100 ma 50 v 6b595 10-bit (active pull-downs) -25 ma 60 v 5810-f and 6810 12-bit (active pull-downs) -25 ma 60 v 5811 16-bit (constant-current led driver) 75 ma 17 v 6276 20-bit (active pull-downs) -25 ma 60 v 5812-f and 6812 32-bit (active pull-downs) -25 ma 60 v 5818-f and 6818 32-bit 100 ma 30 v 5833 32-bit (saturated drivers) 100 ma 40 v 5832 parallel-input latched drivers 4-bit 350 ma 50 v? 5800 8-bit -25 ma 60 v 5815 8-bit 350 ma 50 v? 5801 8-bit (dmos drivers) 100 ma 50 v 6b273 8-bit (dmos drivers) 250 ma 50 v 6273 special-purpose devices unipolar stepper motor translator/driver 1.25 a 50 v? 5804 addressable 8-bit decoder/dmos driver 250 ma 50 v 6259 addressable 8-bit decoder/dmos driver 350 ma 50 v? 6a259 addressable 8-bit decoder/dmos driver 100 ma 50 v 6b259 addressable 28-line decoder/driver 450 ma 30 v 6817 * current is maximum specified test condition, voltage is maximum rating. see specification for sustaining voltage limits. negative current is defined as coming out of (sourcing) the output. ? complete part number includes additional characters to indicate operating temperature range and package style. internal transient-suppression diodes included for inductive-load protection.
|
